aag 373 38 21 1 314
2
4
6
8
10
12
14
16
18
20
22
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34
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38
40
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78 1
80 633
82 639
84 645
86 651
88 657
90 663
92 669
94 675
96 681
98 687
100 693
102 699
104 705
106 711
108 717
110 723
112 729
114 735
116 741
118 747
276
120 81 78
122 80 78
124 121 78
126 83 78
128 82 78
130 127 78
132 85 78
134 84 78
136 133 78
138 87 78
140 86 78
142 139 78
144 89 78
146 88 78
148 145 78
150 91 78
152 90 78
154 151 78
156 93 78
158 92 78
160 157 78
162 95

... [truncated 5.6 kB]

[16] ^
                    controllable_c[17] ^
                    controllable_c[18];

  initial
  begin
    counter = 0;
  end

  always @ (posedge clk)
  begin
    if(counter[19] & ctrl_xor)
       counter[19] = 0;
    else if(counter[18])
      begin
       counter[19] = 1;
       counter[18] = 0;
      end
    else
       counter[18:0] = a;
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 8/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 0.012 [SYNTCOMP2014-RealSeq]
#.