aag 142 2 21 1 119
2
4
6 1
8 131
10 139
12 147
14 155
16 163
18 171
20 179
22 187
24 195
26 203
28 211
30 219
32 227
34 235
36 243
38 251
40 259
42 267
44 275
46 284
124
48 46 6
50 44 6
52 42 6
54 40 6
56 38 6
58 36 6
60 34 6
62 32 6
64 30 6
66 28 6
68 26 6
70 24 6
72 22 6
74 20 6
76 18 6
78 16 6
80 14 6
82 12 6
84 8 6
86 10 6
88 86 84
90 88 82
92 90 80
94 92 78
96 94 76
98 96 74
100 98 72
102 100 70
104 102 68
106 104 66
108 106 64
110 108 62
112 110 60
114 112 58
116 114 56
118 116 54
120 118 52
122 120 5

... [truncated 1.9 kB]

t;
  output err;
  reg [19:0] counter;

  assign err = (counter == 20'b11111111111111111111) ? 1 : 0;

  initial
  begin
    counter = 20'b0;
  end
  always @ (posedge clk)
  begin
    if(stay)
      counter = counter;
    else if(counter == 20'b01111111111111111111 && controllable_reset)
      counter = 0;
    else
      counter = counter + 1;
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 7/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 8.16051 [SYNTCOMP2014-RealSeq]
#.