aag 163 2 11 1 150
2
4
6 1
8 273
10 279
12 285
14 291
16 297
18 303
20 309
22 315
24 321
26 327
104
28 9 6
30 8 6
32 29 6
34 11 6
36 10 6
38 35 6
40 13 6
42 12 6
44 41 6
46 15 6
48 14 6
50 47 6
52 17 6
54 16 6
56 53 6
58 19 6
60 18 6
62 59 6
64 21 6
66 20 6
68 65 6
70 23 6
72 22 6
74 71 6
76 25 6
78 24 6
80 77 6
82 27 6
84 26 6
86 83 6
88 38 32
90 88 44
92 90 50
94 92 56
96 94 62
98 96 68
100 98 74
102 100 80
104 102 86
106 102 85
108 106 4
110 108 3
112 111 3
114 109 3
116 115 112
118 109 33
120 30 2
122 1

... [truncated 1.9 kB]

 controllable_reset;
  output err;
  reg [9:0] counter;

  assign err = (counter == 10'b1111111111) ? 1 : 0;
  
  initial
  begin
    counter = 10'b0;
  end
  always @ (posedge clk)
  begin
    if(stay)
      counter = counter;
    else if(counter == 10'b0111111111 && controllable_reset)
      counter = 0;
    else
      counter = counter + 1;
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 8/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 0.016001 [SYNTCOMP2014-RealSeq]
#.