aag 188 22 13 1 153
2
4
6
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10
12
14
16
18
20
22
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46 1
48 187
50 202
52 220
54 238
56 256
58 274
60 292
62 310
64 328
66 346
68 364
70 376
116
72 48 46
74 50 46
76 74 72
78 52 46
80 78 76
82 54 46
84 82 80
86 56 46
88 86 84
90 58 46
92 90 88
94 60 46
96 94 92
98 62 46
100 98 96
102 64 46
104 102 100
106 66 46
108 106 104
110 68 46
112 110 108
114 70 46
116 114 112
118 4 3
120 5 2
122 121 119
124 122 6
126 123 7
128 127 125
130 128 8
132 129 9
134 133 131
136 134 10
138 135 11

... [truncated 2.9 kB]

ble_c[6] ^
                    controllable_c[7] ^
                    controllable_c[8] ^
                    controllable_c[9] ^
                    controllable_c[10];

  initial
  begin
    counter = 0;
  end

  always @ (posedge clk)
  begin
    if(counter[11] & ctrl_xor)
       counter[11] = 0;
    else
       counter = counter + {1'b0, a};
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 8/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 0.012 [SYNTCOMP2014-RealSeq]
#.