aag 3321 77 96 1 3148
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... [truncated 218.4 kB]

TY =  i_nEMPTY;
   reg_controllable_ENQ =  controllable_ENQ;
   reg_controllable_DEQ =  controllable_DEQ;
   reg_controllable_SLC0 =  controllable_SLC0;
   reg_controllable_SLC1 =  controllable_SLC1;
   reg_controllable_SLC2 =  controllable_SLC2;
   reg_controllable_SLC3 =  controllable_SLC3;
   reg_controllable_SLC4 =  controllable_SLC4;

 end
endmodule

-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 3/3 [2015-pre-classification]
SOLVED_IN : 4.47736 [2015-pre-classification]
#.