aag 177 2 26 1 149
2
4
6 1
8 161
10 169
12 177
14 185
16 193
18 201
20 209
22 217
24 225
26 233
28 241
30 249
32 257
34 265
36 273
38 281
40 289
42 297
44 305
46 313
48 321
50 329
52 337
54 345
56 354
154
58 56 6
60 54 6
62 52 6
64 50 6
66 48 6
68 46 6
70 44 6
72 42 6
74 40 6
76 38 6
78 36 6
80 34 6
82 32 6
84 30 6
86 28 6
88 26 6
90 24 6
92 22 6
94 20 6
96 18 6
98 16 6
100 14 6
102 12 6
104 8 6
106 10 6
108 106 104
110 108 102
112 110 100
114 112 98
116 114 96
118 116 94
120 118 92
122 120 90
124 122 88
12

... [truncated 2.4 kB]

t err;
  reg [24:0] counter;

  assign err = (counter == 25'b1111111111111111111111111) ? 1 : 0;

  initial
  begin
    counter = 25'b0;
  end
  always @ (posedge clk)
  begin
    if(stay)
      counter = counter;
    else if(counter == 25'b0111111111111111111111111 && controllable_reset)
      counter = 0;
    else
      counter = counter + 1;
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 3/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 311.767 [SYNTCOMP2014-RealSeq]
#.