aag 323 2 21 1 300
2
4
6 1
8 533
10 539
12 545
14 551
16 557
18 563
20 569
22 575
24 581
26 587
28 593
30 599
32 605
34 611
36 617
38 623
40 629
42 635
44 641
46 647
204
48 9 6
50 8 6
52 49 6
54 11 6
56 10 6
58 55 6
60 13 6
62 12 6
64 61 6
66 15 6
68 14 6
70 67 6
72 17 6
74 16 6
76 73 6
78 19 6
80 18 6
82 79 6
84 21 6
86 20 6
88 85 6
90 23 6
92 22 6
94 91 6
96 25 6
98 24 6
100 97 6
102 27 6
104 26 6
106 103 6
108 29 6
110 28 6
112 109 6
114 31 6
116 30 6
118 115 6
120 33 6
122 32 6
124 121 6
126 35 6
128 34

... [truncated 3.8 kB]

t;
  output err;
  reg [19:0] counter;

  assign err = (counter == 20'b11111111111111111111) ? 1 : 0;

  initial
  begin
    counter = 20'b0;
  end
  always @ (posedge clk)
  begin
    if(stay)
      counter = counter;
    else if(counter == 20'b01111111111111111111 && controllable_reset)
      counter = 0;
    else
      counter = counter + 1;
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 7/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 8.15651 [SYNTCOMP2014-RealSeq]
#.