aag 107 2 16 1 89
2
4
6 1
8 101
10 109
12 117
14 125
16 133
18 141
20 149
22 157
24 165
26 173
28 181
30 189
32 197
34 205
36 214
94
38 36 6
40 34 6
42 32 6
44 30 6
46 28 6
48 26 6
50 24 6
52 22 6
54 20 6
56 18 6
58 16 6
60 14 6
62 12 6
64 8 6
66 10 6
68 66 64
70 68 62
72 70 60
74 72 58
76 74 56
78 76 54
80 78 52
82 80 50
84 82 48
86 84 46
88 86 44
90 88 42
92 90 40
94 92 38
96 64 2
98 65 3
100 99 97
102 64 3
104 103 66
106 102 67
108 107 105
110 68 3
112 111 62
114 110 63
116 115 113
118 70 3
120 119 60
12

... [truncated 1.4 kB]

le_reset;
  output err;
  reg [14:0] counter;

  assign err = (counter == 15'b111111111111111) ? 1 : 0;
  
  initial
  begin
    counter = 15'b0;
  end
  always @ (posedge clk)
  begin
    if(stay)
      counter = counter;
    else if(counter == 15'b011111111111111 && controllable_reset)
      counter = 0;
    else
      counter = counter + 1;
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 8/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 0.196011 [SYNTCOMP2014-RealSeq]
#.