aag 649 6 33 1 610
2
4
6
8
10
12
14 1
16 339
18 531
20 627
22 723
24 771
26 819
28 867
30 915
32 939
34 963
36 987
38 1011
40 1035
42 1059
44 1083
46 1107
48 1119
50 1131
52 1143
54 1155
56 1167
58 1179
60 1191
62 1203
64 1215
66 1227
68 1239
70 1251
72 1263
74 1275
76 1287
78 1299
80
80 17 14
82 16 14
84 83 14
86 18 14
88 20 14
90 86 4
92 88 5
94 93 91
96 22 14
98 24 14
100 96 4
102 98 5
104 103 101
106 95 6
108 105 7
110 109 107
112 26 14
114 28 14
116 112 4
118 114 5
120 119 117
122 30 14
124 32 14
126 1

... [truncated 8.1 kB]

  wire [31:0] t4;
  
  assign t1 = s[0] ? {i[30:0],i[31:31]} : i;    // shift by 1 pos
  assign t2 = s[1] ? {t1[29:0],t1[31:30]} : t1; // shift by 2 pos
  assign t3 = s[2] ? {t2[27:0],t2[31:28]} : t2; // shift by 4 pos
  assign t4 = s[3] ? {t3[23:0],t3[31:24]} : t3; // shift by 8 pos
  assign o  = s[4] ? {t4[15:0],t4[31:16]} : t4; // shift by 16 pos
endmodule

-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 7/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 0.016001 [SYNTCOMP2014-RealSeq]
#.