aag 278 5 17 1 256
2
4
6
8
10
12 1
14 173
16 269
18 317
20 365
22 389
24 413
26 437
28 461
30 473
32 485
34 497
36 509
38 521
40 533
42 545
44 557
46
46 15 12
48 16 12
50 48 4
52 18 12
54 52 5
56 55 51
58 57 6
60 20 12
62 60 4
64 22 12
66 64 5
68 67 63
70 69 7
72 71 59
74 73 8
76 24 12
78 76 4
80 26 12
82 80 5
84 83 79
86 85 6
88 28 12
90 88 4
92 30 12
94 92 5
96 95 91
98 97 7
100 99 87
102 101 9
104 103 75
106 105 10
108 32 12
110 108 4
112 34 12
114 112 5
116 115 111
118 117 6
120 36 12
122 120 4
124 38 1

... [truncated 3.5 kB]

  output [15:0] o;
  input [3:0] s;
  wire [15:0] t1;
  wire [15:0] t2;
  wire [15:0] t3;
  
  assign t1 = s[0] ? {i[14:0],i[15:15]} : i;    // shift by 1 pos
  assign t2 = s[1] ? {t1[13:0],t1[15:14]} : t1; // shift by 2 pos
  assign t3 = s[2] ? {t2[11:0],t2[15:12]} : t2; // shift by 4 pos
  assign o  = s[3] ? {t3[7:0],t3[15:8]} : t3; // shift by 8 pos
endmodule

-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 8/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 0.008 [SYNTCOMP2014-RealSeq]
#.