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s file)
Content of add8.v:
// realizable
module bench(clk, a, b, controllable_c, err);
  input clk;
  input [7:0] a;
  input [7:0] b;
  input [7:0] controllable_c;
  output err;
  reg err;

  initial
  begin
    err = 1'b0;
  end

  always @ (posedge clk)
  begin
    if(controllable_c == a + b)
         err = 1'b0;
      else
         err = 1'b1;
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 8/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 0.008 [SYNTCOMP2014-RealSeq]
#.