aag 427 60 2 1 365
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122 1
124 855
126
126 124 122
128 82 43
130 83 42
132 131 129
134 82 42
136 133 3
138 132 2
140 139 137
142 85 45
144 142 134
146 84 45
148 146 135
150 149 145
152 85 44
154 152 135
156 155 150
158 84 44
160 158 134
162 161 156
164 163 5
166 162 4
168 167 165
170 134 84
172 134 44
174 173 171
176 174 159


... [truncated 5.1 kB]


Content of add20.v:
// realizable
module bench(clk, a, b, controllable_c, err);
  input clk;
  input [19:0] a;
  input [19:0] b;
  input [19:0] controllable_c;
  output err;
  reg err;

  initial
  begin
    err = 1'b0;
  end

  always @ (posedge clk)
  begin
    if(controllable_c == a + b)
         err = 1'b0;
      else
         err = 1'b1;
   end
endmodule
-------------------------------
#!SYNTCOMP
STATUS : realizable
SOLVED_BY : 7/8 [SYNTCOMP2014-RealSeq]
SOLVED_IN : 0.036001 [SYNTCOMP2014-RealSeq]
#.